Leaded multi-layer ceramic capacitor with low ESL and low ESR
US8331078B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2010 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Feb 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3426
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multi-layered ceramic capacitor with at least one chip and with first base metal plates in a parallel spaced apart relationship and second base metal plates in a parallel spaced apart relationship wherein the first plates and second plates are interleaved. A dielectric is between the first base metal plates and said second base metal plates and the dielectric has a first coefficient of thermal expansion. A first termination is in electrical contact with the first plates and a second termination is in electrical contact with the second plates. Lead frames are attached to, and in electrical contact with, the terminations wherein the lead frames have a second coefficient of thermal expansion and the second coefficient of thermal expansion is higher than said first coefficient of thermal expansion. The lead frame is a non-ferrous material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.