Charge retention circuit for a time measurement
US8331203B2 · kind B2 · utility
11Cited by
18References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 20, 2007 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Jul 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic charge retention circuit for time measurement, including: at least a first capacitive element, a first electrode of which is connected to a floating node (F); at least a second capacitive element, a first electrode of which is connected to the floating node, the first capacitive element having a leakage through its dielectric space and the second capacitive element having a capacitance greater than the first; and at least a first transistor having an isolated control terminal connected to the floating node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.