Phase control block for managing multiple clock domains in systems with frequency offsets
US8331512B2 · kind B2 · utility
16Cited by
2References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2007 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Nov 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit for performing clock recovery according to a received digital signal (30). The circuit includes at least an edge sampler (105) and a data sampler (145) for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock (25) and data clock (20) signals offset in phase from one another to the respective clock inputs of the edge sampler (105) and the data sampler (145). The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.