Multi-stage command processing pipeline and method for shared cache access
US8332590B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2009 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Jan 20, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A command processing pipeline is coupled to a shared cache. The command processing pipeline comprises (i) a first command processing stage configured to sequentially receive and process first and second cache commands, and (ii) a second command processing stage coupled to the first command processing stage. The first and the second command processing stages are two consecutive command processing stages of the command processing pipeline. The first and second command processing stages may access different groups of cache resources, and the first and second cache commands may be processed during consecutive clock cycles of a clock signal. Processing of the second cache command may be performed independently of an outcome of processing the first cache command by the first command processing stage. A third command processing stage may write data associated with the first cache command to one of a valid memory and a data memory included in the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.