Error-correcting code and process for fast read-error correction
US8332731B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2009 |
| Grant date | Dec 11, 2012 |
| Priority date | — |
| Expiry date | Mar 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1575
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Subject matter, for example, disclosed herein relates to an embodiment of a process, system, device, or article involving error correction codes. In a particular embodiment, an error-correcting device may comprise an input port to receive an error correcting code (ECC) based, at least in part, on contents of a memory array; a nonlinear computing block to process the ECC to provide a plurality of signals representing a nonlinear portion of an error locator polynomial; and a linear computing block to process the ECC concurrently with processing the ECC to provide a plurality of signals representing the nonlinear portion of the error locator polynomial, to provide a plurality of signals representing a linear portion of the error locator polynomial.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.