Method of fabricating a plurality of gate structures
US8334198B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2011 |
| Grant date | Dec 18, 2012 |
| Priority date | — |
| Expiry date | Apr 12, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.