Power semiconductor device and manufacturing method therefor
US8334598B2 · kind B2 · utility
2Cited by
2References
6Claims
0Family size
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Inventors
Key dates
| Filing date | Aug 25, 2010 |
| Grant date | Dec 18, 2012 |
| Priority date | — |
| Expiry date | Nov 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power semiconductor device includes a substrate, an element circuit pattern formed on the substrate and made of Cu covered with an electroless Ni—P plating layer, and a power semiconductor element bonded to the element circuit pattern by a solder, wherein the solder is an alloy of Sn, Sb, and Cu, and the weight percent of Cu is in the range of 0.5 to 1%, inclusive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.