Cache memory system for a data processing apparatus
US8335122B2 · kind B2 · utility
19Cited by
2References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2008 |
| Grant date | Dec 18, 2012 |
| Priority date | — |
| Expiry date | Sep 16, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.