Gregory K. Chen
64Patents
8h-index
42Co-inventors
74Inventor score
Filing activity: Nov 12, 2008 → Aug 24, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8335122B2 | Cache memory system for a data processing apparatus | Emerging Cross-Sectional Technologies | 19 | Active |
| US10642922B2 | Binary, ternary and bit serial compute-in-memory circuits | Physics | 15 | Active |
| US8593171B2 | Power supply monitor | Physics | 13 | Active |
| US8564275B2 | Reference voltage generator having a two transistor design | Physics | 12 | Active |
| US9652425B2 | Method, apparatus and system for a source-synchronous circuit-switched network on a chip (NOC) | Emerging Cross-Sectional Technologies | 10 | Active |
| US11048434B2 | Compute in memory circuits with time-to-digital computation | Physics | 9 | Active |
| US10922607B2 | Event driven and time hopping neural network | Physics | 8 | Active |
| US10860682B2 | Binary, ternary and bit serial compute-in-memory circuits | Physics | 8 | Active |
| US9979668B2 | Combined guaranteed throughput and best effort network-on-chip | Emerging Cross-Sectional Technologies | 7 | Active |
| US10748603B2 | In-memory multiply and accumulate with global charge-sharing | Physics | 7 | Active |
| US11061646B2 | Compute in memory circuits with multi-Vdd arrays and/or analog multipliers | Physics | 7 | Active |
| US9680765B2 | Spatially divided circuit-switched channels for a network-on-chip | Electricity | 6 | Active |
| US10825509B2 | Full-rail digital read compute-in-memory circuit | Physics | 5 | Active |
| US10831446B2 | Digital bit-serial multi-multiply-and-accumulate compute in memory | Physics | 4 | Active |
| US10565138B2 | Memory device with multiple memory arrays to facilitate in-memory computation | Emerging Cross-Sectional Technologies | 3 | Active |
| US8407025B2 | Operating parameter control of an apparatus for processing data | Emerging Cross-Sectional Technologies | 3 | Active |
| US11151046B2 | Programmable interface to in-memory cache processor | Physics | 2 | Active |
| US10713558B2 | Neural network with reconfigurable sparse connectivity and online learning | Physics | 2 | Active |
| US9634866B2 | Architecture and method for hybrid circuit-switched and packet-switched router | Electricity | 2 | Active |
| US11138499B2 | Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits | Physics | 2 | Active |
| US10877752B2 | Techniques for current-sensing circuit design for compute-in-memory | Physics | 2 | Active |
| US11347477B2 | Compute in/near memory (CIM) circuit architecture for unified matrix-matrix and matrix-vector computations | Physics | 1 | Active |
| US11062203B2 | Neuromorphic computer with reconfigurable memory mapping for various neural network topologies | Physics | 1 | Active |
| US10884957B2 | Pipeline circuit architecture to provide in-memory computation functionality | Emerging Cross-Sectional Technologies | 1 | Active |
| US11726950B2 | Compute near memory convolution accelerator | Emerging Cross-Sectional Technologies | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.