Patent · US Active

Method of manufacture transistor with reduced charge carrier mobility

US8338251B2 · kind B2 · utility

8Cited by

1References

10Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Joerg Berthold · Munich, DE
Christian Pacha · Birkenfeld, DE
Klaus von Arnim · Munich, DE

Key dates

Filing date	May 16, 2012
Grant date	Dec 25, 2012
Priority date	—
Expiry date	May 16, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/40
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.