Systems and methods for vertically integrating semiconductor devices
US8338267B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2007 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Feb 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01033
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems and methods for vertically integrating semiconductor devices are described. In one embodiment, a method comprises providing an interposer, aligning and bonding a plurality of die to a first surface of the interposer, aligning and bonding a backplate to the plurality of die, and reducing at least one portion of the interposer to create a reconstituted wafer. In another embodiment, an apparatus comprises an interposer operable to receive at least one donor semiconductor device disposed on a first surface of the interposer and aligned therewith, and at least one host semiconductor device disposed on a second surface of the interposer and aligned therewith; where the interposer allows the at least one donor and host semiconductor devices to become vertically integrated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.