Reduced pattern loading for doped epitaxial process and semiconductor structure
US8338279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2011 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | May 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0128
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.