Semiconductor device and manufacturing method thereof

US8338831B2 · kind B2 · utility

Assignee

• FUJITSU SEMICONDUCTOR LIMITED · JP

Inventors

• Naoyoshi Tamura · Kawasaki, JP
• Yosuke Shimamune · Kawasaki, JP
• Hirotaka Maekawa · Kawasaki, JP

Key dates

• Filing date: Jun 29, 2010
• Grant date: Dec 25, 2012
• Expiry date: Dec 3, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

Recesses are formed in a pMOS region 2, and a SiGe layer is then formed so as to cover a bottom surface and a side surface of each of the recesses. Next, a SiGe layer containing Ge at a lower content than that in the SiGe layer is formed on each of the SiGe layers.