Stacked-type chip package structure and fabrication method thereof
US8338929B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2008 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Oct 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked-type chip package structure in which stacked chips and stacked flexible circuit boards are disposed on a substrate. A plurality of spacer layers is respectively sandwiched between two adjacent chips and stacked on top of each other. In addition, conductive bumps are disposed on the substrate and between the stacked flexible circuit boards, such that the stacked flexible circuit boards are electrically connected to the substrate. Besides, conductive wires are electrically connected between the flexible circuit boards and the chips, so as to form a package structure with multi-layer chips on the substrate. Thereby, electrical performance and reliability of the chips are improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.