Semiconductor packages and methods of fabricating the same
US8338941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2010 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Jan 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package may include a substrate having first and second surfaces, the second surface including a recessed portion, a first semiconductor chip mounted on the first surface, a first ball land outside the recessed portion, a connection pad inside the recessed portion, a second chip in the recessed portion, the second semiconductor chip including a through via electrically connected to the connection pad, and a second ball land electrically connected to the through via. A semiconductor package may include a substrate having first and second surfaces, the second surface including a recessed portion, a first semiconductor chip mounted on the first surface, a first ball land outside the recessed portion, a connection pad inside the recessed portion, a second semiconductor chip in the recessed portion, the second chip including a through via electrically connected to the connection pad, and a second ball land electrically connected to the through via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.