Power savings and/or dynamic power management in a memory
US8339891B2 · kind B2 · utility
18Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2010 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Jul 7, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a plurality of buffers and a memory controller. The plurality of buffers may each be configured to generate an access request signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients. The memory controller circuit may be configured to generate a clock enable signal in response to the plurality of access request signals. The clock enable signal may be configured to initiate entering and exiting a power savings mode of a memory circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.