Device and method for scheduling transactions over a deep pipelined component
US8341322B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2007 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Oct 28, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device and a method, the device has transaction scheduling capabilities, and includes: (i) a memory unit adapted to output data at a first data rate, (ii) a data transaction initiator adapted to receive data at a second data rate that is lower than the first data rate; (iii) a deep pipelined crossbar characterized by a latency; and (iv) a data rate converter connected between the deep pipelined crossbar and the data transaction initiator; wherein the data rate converter is adapted to schedule a transaction of data unit from the memory unit in response to the latency of the deep pipelined crossbar, the first data rate, the second data rate, and size of an available storage space, within the data rate converter allocated for storing data from the memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.