Microprocessor comprising signature means for detecting an attack by error injection
US8341475B2 · kind B2 · utility
3Cited by
55References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2011 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Mar 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for monitoring the execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes. Current cumulative signatures are produced using deterministic address, control or data logic signals involved in the execution of the sequence and taken off at various points of the integrated circuit. A final cumulative signature is compared with an expected signature and an error signal is produced if the two signatures are not identical. Particularly useful to secure integrated circuits for smart cards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.