Semiconductor layer forming method and structure
US8341588B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2010 |
| Grant date | Dec 25, 2012 |
| Priority date | — |
| Expiry date | Dec 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures. The second semiconductor device comprises the additional structure layer located within the second insertion point location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.