Single poly NVM devices and arrays
US8344443B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2008 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Feb 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-poly non-volatile memory includes a PMOS select transistor (210) formed with a select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well region (240), a serially connected PMOS floating gate transistor (220) formed with part of a p-type floating gate layer (222) and P+ source and drain regions (221, 223) formed in the shared n-well region (240), and a coupling capacitor (230) formed over a p-well region (250) and connected to the PMOS floating gate transistor (220), where the coupling capacitor (230) includes a first capacitor plate formed with a second part of the p-type floating gate layer (222) and an underlying portion of the p-well region (250).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.