Distributing power with through-silicon-vias
US8344496B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2009 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Nov 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit with distributed power using through-silicon-vias (TSVs) is presented. The integrated circuit has conducting pads for providing power and ground located within the peripheral region of the top surface. A number of through-silicon-vias are distributed within the peripheral region and a set of TSVs are formed within the non-peripheral region of the integrated circuit. Conducting lines on the bottom surface are coupled between each peripheral through-silicon-via and a corresponding non-peripheral through-silicon-via. Power is distributed from the conducting pads to the TSVs within the non-peripheral region through the TSVs within the peripheral region, thus supplying power and ground to circuits located within the non-peripheral region of the integrated circuit chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.