Semiconductor package and electronic device having the same
US8344497B2 · kind B2 · utility
1Cited by
9References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2008 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Jun 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.