Three-dimensional silicon interposer for low voltage low power systems
US8344512B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 2009 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Oct 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Scalable silicon (Si) interposer configurations that support low voltage, low power operations are provided. In one aspect, a Si interposer is provided which includes a plurality of through-silicon vias (TSVs) within a first plane thereof adapted to serve as power, ground and signal interconnections throughout the first plane such that the TSVs that serve as the power and ground interconnections are greater in number and/or size than the TSVs that serve as the signal interconnections; and a plurality of lines within a second plane of the interposer in contact with one or more of the TSVs in the first plane, the second plane being adjacent to the first plane, adapted to serve as power, ground and signal interconnections throughout the second plane such that the lines that serve as the power and the ground interconnections are greater in number and/or size than the lines that serve as the signal interconnections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.