Delay circuit and method for delaying signal
US8344783B2 · kind B2 · utility
2Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2010 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Mar 31, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/05
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.