Data-aware dynamic supply random access memory
US8345504B2 · kind B2 · utility
12Cited by
6References
10Claims
0Family size
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Key dates
| Filing date | Jan 19, 2011 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Jul 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.