Patent · US Active

Simulating an operation of a digital circuit

US8346527B2 · kind B2 · utility

2Cited by

6References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Joerg Walter · Lörrach, DE
Lothar Felten · Hauset, BE
Volker Urban · Gummersbach, DE
Norbert Schumacher · Bad Liebenzell, DE
Marcel Naggatz · Coswig, DE

Key dates

Filing date	Jan 9, 2009
Grant date	Jan 1, 2013
Priority date	—
Expiry date	Jun 9, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/3312
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for simulating an operation of a digital circuit (01) is described. The method utilizes cycle simulation, wherein in a cycle based simulation model (34) of the digital circuit (01) components (02, 03, 04, 05) of the digital circuit (01) are clocked synchronously every cycle (19) of a functional clock (Clk). According to the invention, real digital circuit (01), i.e. chip or combinatorial logic (01), timing information is included in the cycle simulation by inserting delay latches (15, 16, 17) into the cycle based simulation model (34) of the digital circuit (01), wherein a non-functional clock (Sim clock) is used to clock the delay latches (15, 16, 17), so that each delay latch (15, 16, 17) delays the propagation of a signal (I, J, K) by a cycle (20) of the non-functional clock (Sim clock).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.