Instruction pre-decoding of multiple instruction sets
US8347067B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2008 |
| Grant date | Jan 1, 2013 |
| Priority date | — |
| Expiry date | Aug 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3865
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus is provided with pre-decoding circuitry 10 serving to generate pre-decoded instructions which are stored within an instruction cache 20. The pre-decoded instructions from the instruction cache 20 are read by decoding circuitry 45, 50, 46 and used to form control signals for controlling processing operations corresponding to the pre-decoded instructions. The program instructions originally fetched can belong to respective ones of a plurality of instruction sets. Instructions from one instruction set are pre-decoded by the pre-decoding circuitry 10 into pre-decoded instructions having a shared format to represent shared functionality with corresponding instructions taken from another of the instruction sets. In this way, a shared portion of the decoding circuitry can generate control signals with respect to the shared functionality of instructions from both of these different instruction sets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.