Method for fabricating metal gate transistor and polysilicon resistor
US8349682B2 · kind B2 · utility
3Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2012 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | May 2, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
Abstract
An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.