Patent · US Active

Shielding techniques for an integrated circuit

US8349710B2 · kind B2 · utility

0Cited by
2References
11Claims
0Family size

Assignee

Inventor

Key dates

Filing dateOct 25, 2010
Grant dateJan 8, 2013
Priority date—
Expiry dateOct 25, 2030

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/14
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Described herein are techniques for forming, during wafer processing, a conductive shielding layer for a chip formed from a wafer. The conductive shielding layer can be formed on multiple sides of a chip prior to dicing the wafer to separate the chip from the wafer. A wafer may be processed to form trenches that extend substantially through the wafer. The trenches may be formed opposite scribe lines that identify boundaries between chips of the wafer and may extend through the wafer toward the scribe lines. A shielding layer may be formed along the trenches.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.