Flipchip bump patterns for efficient I-mesh power distribution schemes
US8350375B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2008 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Jul 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a flipchip scheme where power and ground bumps are arranged in a striped configuration. Specifically, there are a plurality of lines of power bumps, and a plurality of lines of ground bumps. Each line of power bumps is interconnected by a mesh core power bus, and each line of ground bumps is interconnected by a mesh core ground bus. The busses are shorted across the bumps without having to use metal tab extensions. This arrangement provides that: signal routing can be provided between the lines of bumps; and/or the mesh core power busses can be provided as being wider in order to provide improved power mesh performance and/or in order to reduce or eliminate the metal required on the second top-most metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.