Anwar Ali
25Patents
7h-index
26Co-inventors
65Inventor score
Filing activity: May 14, 1999 → Jul 23, 2009
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6657870B1 | Die power distribution system | Electricity | 39 | Expired |
| US6836026B1 | Integrated circuit design for both input output limited and core limited integrated circuits | Electricity | 33 | Expired |
| US6671865B1 | High density input output | Electricity | 25 | Expired |
| US6798069B1 | Integrated circuit having adaptable core and input/output regions with multi-layer pad trace conductors | Electricity | 11 | Expired |
| US6591410B1 | Six-to-one signal/power ratio bump and trace pattern for flip chip design | Electricity | 10 | Expired |
| US8350375B2 | Flipchip bump patterns for efficient I-mesh power distribution schemes | Electricity | 8 | Active |
| US7117467B2 | Methods for optimizing package and silicon co-design of integrated circuit | Physics | 8 | Expired |
| US7863716B2 | Method and apparatus of power ring positioning to minimize crosstalk | Electricity | 4 | Active |
| US7107561B2 | Method of sizing via arrays and interconnects to reduce routing congestion in flip chip integrated circuits | Electricity | 3 | Expired |
| US7075179B1 | System for implementing a configurable integrated circuit | Electricity | 3 | Expired |
| US7554133B1 | Pad current splitting | Electricity | 3 | Active |
| US6704918B1 | Integrated circuit routing | Electricity | 3 | Expired |
| US6781228B2 | Donut power mesh scheme for flip chip package | Electricity | 3 | Expired |
| US6998638B2 | Test structure for detecting bonding-induced cracks | Electricity | 2 | Expired |
| US6784102B2 | Laterally interconnecting structures | Electricity | 2 | Expired |
| US6815812B2 | Direct alignment of contacts | Electricity | 2 | Expired |
| US8115321B2 | Separate probe and bond regions of an integrated circuit | Electricity | 2 | Active |
| US6768142B2 | Circuit component placement | Electricity | 2 | Expired |
| US7569472B2 | Method and apparatus of power ring positioning to minimize crosstalk | Electricity | 2 | Active |
| US8151237B2 | Disabling unused IO resources in platform-based integrated circuits | Physics | 2 | Active |
| US6781150B2 | Test structure for detecting bonding-induced cracks | Electricity | 2 | Expired |
| US7328417B2 | Cell-based method for creating slotted metal in semiconductor designs | Electricity | 1 | Expired |
| US7430730B2 | Disabling unused IO resources in platform-based integrated circuits | Physics | 1 | Expired |
| US7737564B2 | Power configuration method for structured ASICs | Electricity | 0 | Expired |
| US6683476B2 | Contact ring architecture | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.