Advanced process control for gate profile control
US8352062B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Mar 11, 2009 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Nov 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; performing a plurality of processes to form a gate stack over the substrate, wherein the gate stack comprises a gate layer; measuring a grain size of the gate layer after at least one of the plurality of processes; determining whether the measured grain size is within a target range; and modifying a recipe of at least one of the plurality of processes if the measured grain size of the gate layer is not within the target range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.