Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy
US8352687B2 · kind B2 · utility
2Cited by
7References
7Claims
0Family size
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Key dates
| Filing date | Jun 23, 2010 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Mar 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache includes a cache pipeline, a request receiver configured to receive off chip coherency requests from an off chip cache and a plurality of state machines coupled to the request receiver. The cache also includes an arbiter coupled between the plurality of state machines and the cache pipe line and is configured to give priority to off chip coherency requests as well as a counter configured to count the number of coherency requests sent from the cache pipeline to a lower level cache. The cache pipeline is halted from sending coherency requests when the counter exceeds a predetermined limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.