Dynamic squelch detection power control
US8352764B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2008 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Oct 31, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.