Memory error detection
US8352805B2 · kind B2 · utility
41Cited by
101References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2009 |
| Grant date | Jan 8, 2013 |
| Priority date | — |
| Expiry date | Feb 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.