Method of fabricating SOI super-junction LDMOS structure capable of completely eliminating substrate-assisted depletion effects

US8354330B2 · kind B2 · utility

Assignee

• SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY CHINESE ACADEMY OF SCIENCES · CN

Inventors

• Xinhong Cheng · Shanghai, CN
• Dawei He · Cupertino, US
• Zhongjian Wang · Nanhu, CN
• Dawei Xu · Inagi, JP
• Chao Xia · 红钢城街道, CN
• Zhaorui Song · Shanghai, CN
• Yuehui Yu · Shanghai, CN

Key dates

• Filing date: Dec 15, 2010
• Grant date: Jan 15, 2013
• Expiry date: Dec 15, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6758
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present invention relates to a method of fabricating an SOI SJ LDMOS structure that can completely eliminate the substrate-assisted depletion effects, comprising the following steps: step one: a conducting layer is prepared below the SOI BOX layer using the bonding technique; the conducting layer is prepared in the following way: depositing a barrier layer on a first bulk silicon wafer, and then depositing a charge conducting layer, thereby obtaining a first intermediate structure; forming a silicon dioxide layer on a second bulk silicon wafer via thermal oxidation, then depositing a barrier layer, and finally depositing a charge conducting layer, thereby obtaining a second intermediate structure; bonding the first intermediate structure and the second intermediate structure using the metal bonding technology to arrange the conducting layer below the SOI BOX layer; step two: a SJ LDMOS structure is fabricated on the SOI substrate having a conducting layer. The present invention is capable of releasing the charge accumulated at the lower interface of the BOX layer, eliminating the effect of the vertical charge on the charge balance between the p-type pillar and the n-type pillar…