Integrated circuit with adaptive VGG setting
US8354671B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2010 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Dec 8, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/514
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A technique for setting Vgg in an IC is disclosed. The technique includes specifying a design reliability lifetime for the IC, and a relationship between maximum gate bias and gate dielectric thickness for the IC sufficient to achieve the design reliability lifetime is established. The IC is fabricated and the gate dielectric thickness is measured. A maximum gate bias voltage is determined according to the gate dielectric thickness and the relationship between maximum gate bias and gate dielectric thickness, and a Vgg trim circuit of the IC is set to provide Vgg having the maximum gate bias voltage that will achieve the design reliability lifetime according to the measured gate dielectric thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.