Test electronics to device under test interfaces, and methods and apparatus using same
US8354853B2 · kind B2 · utility
0Cited by
7References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2009 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Jan 12, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2889
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In one embodiment, a test system has a set of test electronics for testing a device under test (DUT). The test system also has at least one test electronics to DUT interface having a zero insertion force (ZIF) connector. Each ZIF connector has a ZIF connector to DUT clamping mechanism configured to i) apply a first orthogonal force to a probe card that interfaces with a DUT, by pressing the ZIF connector against the probe card, and simultaneously ii) exert at least one second orthogonal force on the probe card, the at least one second orthogonal force being opposite in direction to the first orthogonal force.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.