PLL start-up circuit
US8354866B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2010 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Jul 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/101
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A start-up circuit for a PLL includes a phase-frequency detector (PFD), one or more logic gates, a flip-flop and a false detection circuit. The false detection circuit includes a set of series connected flip-flops. The PFD receives a reference signal and a feedback signal. The PFD compares the frequency of a reference signal with that of a feedback signal. If the frequency of the reference signal is greater than the frequency of the feedback signal then a start-up signal is generated and transmitted to the PLL. The PLL increases the frequency of the feedback signal until it is greater than the frequency of the reference signal. The generation of the start-up signal is halted when the frequency of the feedback signal is greater than the frequency of the reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.