Predictive phase locked loop system
US8355239B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2009 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Nov 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A phase locked loop (PLL) circuit includes a first signal detector having a first input terminal configured to receive a varying first input signal, a second input terminal configured to receive a feedback signal that corresponds to the center of the input frequency, and an output terminal configured to provide an output signal corresponding to a phase difference between the first input and feedback signals. A delay estimator has an input terminal configured to receive the output signal from the first phase detector and in response thereto, output a phase difference estimation signal. A variable delay circuit has an input terminal configured to receive the phase difference estimation signal and in response thereto, phase shift the second input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.