Method and apparatus for providing a channelized buffer
US8356125B1 · kind B1 · utility
4Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 15, 2008 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Nov 8, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a device is disclosed. For example, in one embodiment of the present invention, the device comprises a first memory stage for storing a plurality of pointer values associated with a plurality of buffers, wherein the plurality of buffers is associated with a plurality of logical channels. The device further comprise a second memory stage, wherein an access address to the second memory stage is formed from a concatenation of one of the plurality of pointer values and a channel number corresponding to one of the plurality of logical channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.