Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriers
US8356166B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2009 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Apr 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/467
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.