Layout testing method and wafer manufacturing method
US8356271B2 · kind B2 · utility
2Cited by
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20Claims
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Key dates
| Filing date | Mar 17, 2011 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Apr 1, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A product layout testing method includes testing and correcting one or more patterns of a product layout, detecting and correcting electrical characteristic changes of transistors of the product layout, and testing whether a product characteristic predicted from the product layout is equal to that predicted from a designed circuit view. Weak points with respect to the pattern may be detected and corrected, electrical characteristic changes depending on layout parameters may be detected and corrected, and whether a circuit operation depending on parasitic components is normal may be checked.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.