Preventing information leakage between components on a programmable chip in the presence of faults
US8356358B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2009 |
| Grant date | Jan 15, 2013 |
| Priority date | — |
| Expiry date | Oct 14, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms are provided to prevent information leakage between components implemented on a programmable chip such as a Field Programmable Gate Array (FPGA). An automated routing algorithm is effective at enforcing security restrictions with minimal input form the user while providing efficient utilization of the device. Compatible sets of signals are identified and locked, and reservations of routing resources are generated. Remaining signals are rerouted until all signal constraints are met. Specified security constraints with one or more security levels and one or more secure regions may be applied through iterations of the automated routing mechanism.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.