Methods of forming integrated circuits
US8357579B2 · kind B2 · utility
7Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2011 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | Mar 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of each of the recesses. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has second type dopants. The second type dopants are opposite to the first type dopants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.