Method of patterning a metal gate of semiconductor device
US8357617B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2009 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | Feb 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.