Integrated circuit system employing low-k dielectrics and method of manufacture thereof
US8358007B2 · kind B2 · utility
12Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2010 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | Sep 15, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.