Semiconductor package featuring flip-chip die sandwiched between metal layers
US8358017B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 5, 2008 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | Aug 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments in accordance with the present invention relate to flip-chip packages for semiconductor devices, which feature a die sandwiched between metal layers. One metal layer comprises portions of the lead frame configured to be in electrical and thermal communication with various pads on a first surface of the die (e.g. IC pads or MOSFET gate or source pads) through a solder ball contact. The other metal layer is configured to be in at least thermal communication with the opposite side of the die. Embodiments of packages in accordance with the present invention exhibit superior heat dissipation qualities, while avoiding the expense of wire bonding. Embodiments of the present invention are particularly suited for packaging of power devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.