Multiple-loop symmetrical inductor
US8358192B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2012 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | May 3, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4902
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A symmetrical inductor includes an integrated circuit having a plurality of conductive layers. A first loop is disposed in an upper layer of the conductive layers, and at least two strapped loops are disposed in at least two layers of the conductive layers, respectively. The strapped loops are coupled in series to the first loop, and the at least two layers are below the upper layer. A second loop is disposed in the upper layer and is coupled in series to the at least two strapped loops. A first terminal electrode is coupled to the first loop, and a second terminal electrode is coupled to the second loop. A center-tap electrode is coupled to the at least two strapped loops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.