Semiconductor device having additive latency
US8358546B2 · kind B2 · utility
34Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Nov 12, 2010 |
| Grant date | Jan 22, 2013 |
| Priority date | — |
| Expiry date | Apr 8, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device receives a command corresponding to a memory access operation and performs the memory access operation after an additive latency period. The additive latency period begins when the command is received. The semiconductor device comprises a phase controller for controlling a phase of a clock signal and outputting a phase-controlled clock signal, and a controller for generating and outputting a control signal for enabling the phase controller that is disabled, at a predetermined time in the additive latency period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.